The present invention concerns a technique for manufacturing a semiconductor integrated circuit device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and, more in particular, it relates to a technique which may be effectively applied to the manufacture of a DRAM (Dynamic Random Access Memory).
In recent years, in manufacturing steps of LSIs based on the deep submicron design rule, since the accuracy of alignment of a stopper has approached its utmost limit, it has become difficult to ensure a mask alignment margin between a contact hole and a gate electrode upon forming a contact hole for the contact of wirings in a source region and a drain region of a MISFET.
As a countermeasure, a SAC (Self Align Contact) technique of forming a contact hole by self alignment using a silicon nitride film having a fine selectivity ratio of about 10 to 20 relative to a silicon oxide film as an etching stopper has attracted some attention. This is a technique of forming a contact hole by forming an insulation film over a gate electrode (cap insulation film) and a side wall insulation film (side wall spacer) with a silicon nitride film and etching a silicon oxide film deposited over the gate electrode, in which scraping of a gate electrode is prevented by using the cap insulation film and the side wall spacer made of silicon nitride as the etching stopper, thereby making it unnecessary for an alignment margin to be provided between the gate electrode and the contact hole.
The SAC technique using the silicon nitride film has been described, for example, in U.S. Pat. No. 5,188,975 (Japanese Patent Laid-Open Hei 4(1992)-342164).